The present disclosure relates to semiconductor structures and, more particularly, to a method of forming a complementary metal oxide semiconductor (CMOS) structure with N-type and P-type field effect transistors (FETs) having symmetric source/drain junctions and, optionally, dual silicides.
Generally, CMOS structures incorporate FETS having different type conductivities (e.g., a N-type field effect transistor (NFET) and a P-type field effect transistor (PFET)). Because P-type and N-type FETs are different in many respects, oftentimes a first region of a substrate (e.g., a region on which NFET(s) are being formed) undergoes processing, while a second region of the substrate (e.g., a region on which PFET(s) are being formed) is masked (e.g., with a lithographically patterned photoresist mask) and vice versa. For example, during epitaxial deposition of raised source/drain regions on FET(s) in the first region, the second region may be masked, and vice-versa. By using discrete epitaxial deposition processes, different dopants, which are optimal for the specific type conductivity of the FET(s) being formed, can be used to in situ dope the raised source/drain regions. Similarly, during metal silicide formation on the source/drain regions of FET(s) in the first region, the second region can be masked and vice-versa. By using discrete metal silicide formation processes, different metals, which are optimal for the specific type conductivity of the FET(s) being formed, can be used. However, using multiple masks and, particularly, photoresist masks and performing discrete processing on different regions of a substrate increase manufacturing costs and overall processing time. Additionally, performing discrete epitaxial deposition processes to form raised source/drain regions, as described above, inherently results in a CMOS structure wherein the NFET(s) and PFET(s) have gate sidewall spacers that are asymmetric (i.e., wherein the gate sidewall spacers on the NFET(s) have a different width than the gate sidewall spacers on the PFET(s)). Consequently, the NFET(s) and PFET(s) have source/drain junctions that are also asymmetric (i.e., have source/drain junctions with different lengths and, thereby different resistances).